Special Topics in CPE:
Verilog HDL Modeling and Synthesis
(ENCE 3830/4500)

Table of Contents:



Announcements

  • ALL ENCE 3830/4500 Students PLEASE make sure that your Verilog HDL labs/programming assignments conform to the programming style guide line found on this web page!!
  • ENCE 3830/4500: Grades
    Administrative Information Lectures
    First 5 weeks Second 5 weeks
    • Week 6:
      • Lecture #10: (Mon. 4/24/00)
      • Midterm Exam: (Wed. 4/26/00)
    • Week 7:
    • Week 8:
    • Week 9:
    • Week 10:
    Homeworks
    First 5 weeks Second 5 weeks
    • Homework #1 / Solution -->
    • Homework #2 / Solution
    • Homework #3 / Solution
    • Homework #4 / Solution
    • Homework #5 / Solution
    • Homework #6 / Solution
    • Homework #7 / Solution
    • Homework #8 / Solution
    In Class Quizes
    First 5 weeks Second 5 weeks
    • Quiz #1 / Solution
    • Quiz #2 / Solution
    • Quiz #3 / Solution
    • Quiz #4 / Solution
    • Quiz #5 / Solution
    • Quiz #6 / Solution
    • Quiz #7 / Solution
    • Quiz #8 / Solution
    Lab Assignments
    First 5 weeks Second 5 weeks
    • Lab Assignment #1
    • Lab Assignment #2
    • Lab Assignment #3
    • Lab Assignment #4
    • Lab Assignment #5
    • Lab Assignment #6
    Final Project Presentation and Report Information Additional Study Notes Miscellaneous Other References Special Topics in CPE: Verilog HDL Modeling and Synthesis
    Informational Resources on the Internet
     

    This page is maintained by Christopher A. Gantz (cgantz@.du.edu).